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EL2019C december 1995 rev g EL2019C fast, high voltage comparator with master slave flip-flop note: all information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ``controlled document''. current revisions, if any, to these specifications are maintained at the factory and are available upon your request. we recommend checking the revision level before finalization of your design documentation. ? 1989 elantec, inc. features # comparator cannot oscillate # fast responsee5 ns data to clock setup, 20 ns clock to output # wide input differential voltage rangee24v on g 15v supplies # wide input common mode voltage rangee g 12v # precision input stagee v os e 1.5 mv # low input bias currente100 na # low input offset currente30 na # g 4.5v to g 18v supplies # 3 state ttl compatible output # no supply current glitch during switching # 103 db voltage gain (low input uncertainty & 30 m v) # 50% power reduction in shut- down mode # input and flip-flop remain active in shutdown mode applications # analog to digital converters # ate pin receiver # zero crossing detector # window detector # ``go/no-go'' detector ordering information part no. temp. range pkg. outline y EL2019Cn b 40 cto a 85 c p-dip mdp0006 general description the el2019 offers a new feature previously unavailable in a comparator beforeea master/slave edge triggered flip-flop. the comparator output will only change output state after a posi- tive going clock edge is applied. thus the output can't feed back to the input and cause oscillation. manufactured with elantec's proprietary complementary bipolar process, this device uses fast pnp and npn transistors in the signal path. a unique circuit design gives the inputs the ability to handle large com- mon mode and differential mode signals, yet retain high speed and excellent accuracy. careful design of the front end insures speed and accuracy when operating with a mix of small and large signals. the three-state output stage is designed to be ttl compatible for any power supply combination, yet it draws a constant current and does not generate current glitches. when the output is disabled, the supply current consumption drops by 50%, but the input stage and master slave flip-flop remain active. elantec facilities comply with mil-i-45208a and other applica- ble quality specifications. for information on elantec's process- ing, see qra1: elantec's processing-monolithic products . connection diagrams 8-pin plastic dip 2019 2 top view free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop absolute maximum ratings (t a e 25 c) v s supply voltage g 18v v in input voltage a v s to b v s d v in differential input voltage limited only by power supplies i in input current (pins 1, 2 or 3) g 10 ma i ins input current (pins 5 or 6) g 5ma p d maximum power dissipation 1.25w (not e 3 - see curves) i op peak output current 50 ma i o continuous output current 25 ma t a operating temperature range b 40 cto a 85 c t j operating junction temperature 150 c t st storage temperature b 65 cto a 150 c important note: all parameters having min/max specifications are guaranteed. the test level column indicates the specific device testing actually performed during production and quality inspection. elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the ltx77 series system. unless otherwise noted, all tests are pulsed tests, therefore t j e t c e t a . test level test procedure i 100% production tested and qa sample tested per qa test plan qcx0002. ii 100% production tested at t a e 25 c and qa sample tested at t a e 25 c, t max and t min per qa test plan qcx0002. iii qa sample tested per qa test plan qcx0002. iv parameter is guaranteed (but not tested) by design and characterization data. v parameter is typical value at t a e 25 c for information purposes only. dc electrical characteristics v s e g 15v, unless otherwise specified parameter description temp limits test level units min typ max v os input offset voltage 25 c 1.5 6 i mv v cm e 0v, v o transition point t min ,t max 8 iii mv i b input bias current 25 c g 100 g 400 i na v cm e 0v, pin 2 or 3 t min ,t max g 600 iii na i os input offset current 25 c 30 150 i na v cm e 0v t min ,t max 250 iii na cmrr common mode rejection 25 c7590 i db ratio (note 1) psrr power supply rejection 25 c7595 i db ratio (note 2) v cm common mode input 25 c g 12 g 13 i v range t min ,t max g 12 iii v v uncer input uncertainty range 30 v m v/rms v ol output voltage logic low 25 c b 0.05 0.15 0.4 i v i ol e 8 ma and i ol e 0 ma) t min ,t max b 0.1 0.4 iii v v oh output voltage logic high v s e g 15v 25 c 3.5 4.0 4.65 i v v s e g 15v t min ,t max 3.5 4.65 iii v v s e g 5v 25 c 2.4 i v v s e g 5v t min 2.4 iii v v s e g 5v t max 2.4 iii v 2 td is 3.6in free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop dc electrical characteristics v s e g 15v, unless otherwise specified e contd. parameter description temp limits test level units min typ max v odis1 v out range, disabled, i ol eb 1ma v s e g 15v 25 c 4.65 i v v s e g 15v t min ,t max 4.65 iii v v s e g 5v 25 c 3.65 v v v odis2 v out range, disabled, i ol ea 1 ma all b 0.3 b 1iiv v s e g 5v to a 15v v inh clock or cs inputs 25 c2 i v logic high input voltage t min ,t max 2 iii v i in clock or cs inputs 25 c g 200 i m a logic input current t min ,t max g 300 iii m a v in e 0v and v in e 5v v inl clock or cs inputs 25 c 0.8 i v logic low input voltage t min ,t max 0.8 iii v i s a en positive supply 25 c 8.8 13 i ma current enabled t min ,t max 14 ii ma i s a dis positive supply 25 c 4.9 6 i ma current disabled t min ,t max 7iima i s b en negative supply 25 c 14.5 17 i ma current enabled t min ,t max 18 ii ma i s b dis negative supply 25 c 6.4 8.0 i ma current disabled t min ,t max 8.0 ii ma ac electrical characteristics v s e g 15v, t a e 25 c parameter description limits test level units min typ max t s setup time 5 mv overdrive 12 20 ii ns t h hold time b 3 0 iv ns t opout clock to output delay 20 25 iv ns t opmin minimum clock width 7 v ns t en output 3-state enable delay 40 70 iv ns t dis output 3-state disable delay 150 300 iv ns note 1: v cm ea 12v to b 12v. note 2: v s e g 5v to g 15v. note 3: the maximum power dissipation depends on package type, ambient temperature and heat sinking. see the typical performance curves for more details. 3 td is 3.8in td is 1.3in free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop typical ac performance curves delay time vs input overdrive supply voltage delay time vs temperature delay time vs vs load capacitor clock to output delay vs temperature minimum clock width vs temperature enabled/disabled times 2019 3 4 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop typical ac performance curves e contd. input bias current vs differential input voltage vs temperature input bias current common mode voltage input bias current vs v o /v i transfer characteristics vs supply voltage supply current vs temperature supply current 2019 4 5 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop typical ac performance curves e contd. v out vs temperature supply voltage v oh vs positive supply voltage v ol vs positive vs ambient temperature maximum power dissipation 8-lead plastic dip 2019 5 6 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop typical ac performance curves e contd. clock time constant clock to output delay vs clock time constant set-up time vs clock time constant psrr vs clock time constant hold time vs clock time constant relative v os shift vs 2019 6 7 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop timing diagram 2019 7 note: since the hold time is negative the input is a don't care at the clock time. this ensures that clock noise will not affect the measurement. block diagram 2019 8 function table inputs internal notes output (time n) (time n b 1) q (time n) a in b in cs clk ab l h normal comparator operation h ba l l with ``d'' flip-flop l ab h h normal comparator operation high z ba h l with ``d'' flip-flop; power down mode high z xxlh qn b 1 data retained in flip-flop qn b 1 xxll qn b 1 data retained in flip-flop qn b 1 xxl qn b 1 data retained in flip-flop qn b 1 xxhh qn b 1 data retained in flip-flop, high z output power down mode xxhl qn b 1 data retained in flip-flop, high z output power down mode xxh qn b 1 data retained in flip-flop, high z output power down mode 8 td is 2.7in free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop application hints device overview the el2019 is the first comparator of its kind. it is capable of 24v differential signals, yet has ex- cellent accuracy, linearity and voltage gain. the el2019 has an internal master/slave flip-flop be- tween the input and output. it even has a 3-state output feature that reduces the power supply cur- rents 50% when the output is disabled, yet the input stage and latch remain active. this ex- tremely fast and accurate device is built with the proprietary elantec complementary bipolar process, which is immune to power sequencing and latch up problems. power supplies the el2019 will work with g 5v to g 18v sup- plies or any combination between (example a 12v and b 5v). the supplies should be well by- passed with good high frequency capacitors (0.01 m f monolithic ceramic recommended) with- in (/4 inch of the power supply leads. good ground plane construction techniques improve stability, and the lead from pin 1 to ground should be short. front end the el2019 uses schottky diodes to make a ``bul- let proof'' front end with very low input bias cur- rents, even if the two inputs are tied to very large differential voltages ( g 24v). the large common mode range ( g 12v mini- mum) and differential voltage handling ability ( g 24v min.) of the device make it useful in ate applications without the need for an input atten- uator with its associated delay. recovery from large overdrives timing accuracy is excellent for all signals with- in the common mode range of the device ( g 12v with g 15v supply). when the common mode range is exceeded the input stage will saturate, input bias currents increase and it may take as much as 200 ns for the device to recover to nor- mal operation after the inputs are returned to the common mode range. if signals greater than the common mode range of the device are anticipat- ed, the inputs should be diode clamped to remain within the common mode range of the device, or the supply voltage be raised to encompass the in- put signal in the common mode range. input slew rate all comparators have input slew rate limitations. the el2019 operates normally with any input slew rate up to 300 v/ m s. input signal slew rates over 300 v/ m s induce offset voltages of 5 mv to 20 mv. this induced offset voltage settles out in about 20 ns, 20 times faster than previous high voltage comparators. this shows up as an in- creased set-up time. master slave flip-flop the built-in master/slave flip-flop only allows the output to change when a positive edge is re- ceived on the clock input. this feature has some major benefits to the user. first, the device can- not oscillate due to feedback from the output to the inputs. second, the device must make a deci- sion when it receives a clock input, and the differ- ence between deciding on a ``0'' or a ``1'' is limited only by the input circuit noise, both internal and external to the el2019. with low impedance sources and a good layout this uncertainty can be less than 30 m v/rms. since a 30 m v change on the input can cause a 4v change on the output this works out to an effective gain of 103 db, more than adequate for a 16-bit analog to digital converter. the hold time of the el2019 is worst case 0 ns, and typically b 3 ns. this means that the analog signal is sampled typically 3 ns before the clock time and, worst case, concurrent with the clock. the el2019 is sensitive to a large clock edge rates. more than a 500 v/ m s edge rate at the clock input will induce v os shifts, reduce psrr, and cause the device to operate incorrectly at low temperatures and low supply voltages. a good method to control the clock edge rate is to place a resistor in series and a capacitor to ground in par- allel with the clock input. generally, any time constant 10 ns or greater will suffice. elantec tests the el2019 with a nominal 20 ns time constant, using a series 330 x resistor and 61 pf of capacitance to ground (including strays). all clocks are generated by schottky ttl and have a 0.25v to 3.5v swing. 9 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop application hints e contd. output stage the output stage of the el2019 is a pair of com- plementary emitter followers operating as a lin- ear amplifier. this makes the output stage of the el2019 glitch free, and improves accuracy and stability when operating with small signals. 3-state output, power saving feature the el2019 has an output stage which can be put into a high impedance ``3-state'' mode. when it is in this mode, the input stage and latch re- main active, yet the device dissipates only 50% of the power used when the output is active. this has advantages in large ate systems where there may be 1000 comparators, but only 10% are in use at any one time. the el2019 will work properly with the chip se- lect input (pin 5) floating, however, good r.f. technique would be to ground this input if it is not used. due to the power saving feature and linear out- put stage, the el2019 does not have a standard ttl 3-state output stage. as such one must be careful when using the 3-state feature with devic- es other than other el2018's or el2019's. when operating from g 15v supplies the 3-state feature is compatible with all ttl families, however cmos families may conflict on high outputs. since the output stage of the el2019 turns on faster than it turns off, a 50 x to 100 x resistor in series with the output will limit fault currents between devices with minimum impact on logic drive capability. typical applications a wide input range window comparator 2019 9 (v in range a 12v to b 12v with v s e g 15v) the el2019 makes an excellent comparator in most analog to digital converters, due to its high gain and fast response. most 2504 based a to d designs can be modified to use the el2019 sim- ply by using an inverted clock to the el2019 as shown below. this results in improved perform- ance due to less jitter of the transition voltages. 2019 11 using the power down/ 3-state feature 2019 10 10 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop burn-in circuit 2019 12 pin numbers are for dip packages. all packages use the same schematic. equivalent schematic 2019 13 11 free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop el2019 macromodel * connections: a input * l b input * ll a v * lll b v * llll cpin * lllll cs * llllll output * lllllll .subckt m2019 2 384657 * * input stage * i1810700 m a r1 13 4 1k r2 14 4 1k q18311qn q28212qn q3 13 11 10 qp q4 14 12 10 qp i2 11 4 200 m a i3 12 4 200 m a * * 2nd stage & flip flop * * i4824700 m a i48241ma q922624qp q10 18 17 24 qp v1 17 0 2.5v q5 15 14 22 qp q6 16 13 22 qp r3 15 4 1k r4 16 4 1k q7 16 15 18 qp q8 15 16 18 qp i5840500 m a q11 41 17 40 qp q1242640qp q13 43 16 41 qp q14 44 15 41 qp q15 44 43 42 qp q16 43 44 42 qp r5 43 4 1k r6 44 4 1k * * output stage * i78352ma s1352050sw d2 35 8 ds i6 26 34 5ma 12 tab wide td is 6.8in free datasheet http://www.datasheetlist.com/
EL2019C fast, high voltage comparator with master slave flip-flop el2019 macromodel e contd. s234450sw d3 34 26 ds q1982021qn2 q204197qp2 r8 21 7 60 r7 20 19 4k q17 19 44 26 qn 5 q1804326qn5 q22 20 20 30 qn 5 q23 19 19 30 qn 8 d1019ds q2101719qp * * power supply current * ips 8 4 4ma * * models * .model qn npn (is e 2e b 15 bf e 400 tf e 0.05ns cje e 0.3pf cjc e 0.2pf ccs e 0.2pf) .model qp pnp (is e 0.6e b 15 bf e 60 tf e 0.3ns cje e 0.5pf cjc e 0.5pf ccs e 0.4pf) .model ds d(is e 2e b 12 tt e 0.05ns eg e 0.62v vj e 0.58) .model sw vswitch (von e 0.4v voff e 2.5v) .ends 13 tab wide td is 3.1in free datasheet http://www.datasheetlist.com/
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EL2019C december 1995 rev g EL2019C fast, high voltage comparator with master slave flip-flop general disclaimer specifications contained in this data sheet are in effect as of the publication date shown. elantec, inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. elantec, inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. elantec, inc. 1996 tarob court milpitas, ca 95035 telephone: (408) 945-1323 (800) 333-6314 fax: (408) 945-9305 european office: 44-71-482-4596 warning e life support policy elantec, inc. products are not authorized for and should not be used within life support systems without the specific written consent of elantec, inc. life support systems are equipment in- tended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. users contemplating application of elantec, inc. products in life support systems are requested to contact elantec, inc. factory headquarters to establish suitable terms & conditions for these applications. elantec, inc.'s warranty is limited to replace- ment of defective components and does not cover injury to per- sons or property or other consequential damages. printed in u.s.a. 16 free datasheet http://www.datasheetlist.com/

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